The present invention relates to integrated circuit devices and methods of operation thereof, and more particularly, to integrated circuit memory devices and methods of operation thereof.
Integrated circuit memory devices, such as nonvolatile memory devices (commonly referred to as xe2x80x9cflashxe2x80x9d memories), typically include a memory cell array divided into plural memory cell blocks, each of the memory cell blocks representing an erase unit. Each memory cell block typically has multiple pages (word lines) to which multiple memory cells are connected.
Generally, rewrite times of such devices are limited by such factors as program erase cycle time. Weak memory cells in the array may be detected by testing the device under predetermined conditions, in what is commonly referred to as a cycling test. In such a test, write and erase operations typically are repeatedly performed under unfavorable conditions. Blocks having one or more cells with excessive leakage current are preferably avoided during a cycling test, because of the high voltage typically used for erasing and writing.
As is well known in the art, a column or row redundancy scheme may be used to repair a memory device with one or more defective memory cells, but the number of cells that need repair can exceed the available number of redundant cells. Even if a device includes an invalid block, however, it can still be used in some applications. The device manufacturer can provide a user with information indicating the invalid block (or information indicating valid blocks) stored in the device itself. Using this information, the user can avoid an invalid block of the device by means of an address mapping (e.g., an invalid block table).
A flow diagram for describing a method of identifying an invalid block in the device according to the prior art is illustrated in FIG. 1. A block addresses BLK applied to the device is initialized to xe2x80x980xe2x80x99 (step S10), and a corresponding block is selected and read (step S11). The data read is checked to determine whether the selected block is valid or invalid (step S12). If the selected block is invalid, an invalid block table is updated (step S13). The invalid block table may be maintained by a computer or other data processing system (e.g., a microcontroller), and stored in a storage device (e.g., a buffer in the microcontroller). If the selected block is valid and the address is not equal to the last address of the device, the address is incremented and a new block is selected and tested (steps S14, S15, S11, S12). This incremental testing continues until all of the memory blocks are checked.
As described above, it is desirable to avoid blocks having cells with high leakage currents when a cycling test is performed. However, if knowledge of these cells is not available or incomplete, a device with such a defect may be classified as a fail device without regard to the number of the invalid memory cell blocks, which can lead to reduced yield in manufacturing.
In light of the foregoing, it is an object of the present invention to provide memory devices and methods of operation thereof in which a status of a memory block can be determined without accessing the memory block.
It is another object of the present invention to provide memory devices and methods of operation thereof in which invalid cells can be identified and avoided during memory cycling tests.
These and other objects, feature and advantages are provided according to the present invention by memory devices and methods of operation thereof in which a decoder circuit is configurable to generate a status signal in response to receipt of an address for a portion, e.g., a block, of a memory array, in lieu of selecting the portion. In this manner, a block containing an invalid cell, e.g., a cell with undesirably high leakage current, can be identified as such during a test such as a cycling test, without actually accessing the block.
According to exemplary embodiments, a configurable decoder circuit includes a plurality of fuse-programmable block decoder circuits, a respective one of which is coupled to a memory block. A block decoder circuit may be configured to a first state in which it is operative, responsive to receipt of an address associated with the corresponding memory block, to select the memory block while generating a first status signal, e.g., a status signal indicating that the block is valid. Alternatively, the block decoder circuit may be configured to a second state in which it is operative, responsive to receipt of the address signal associated with the corresponding memory block, to prevent selection of the memory block while generating a second status signal, e.g., a signal indicating that the block is invalid. The first and second status signals may be provided by taking a signal produced by a status signal generating circuit to a first state or a second state.
According to embodiments of the present invention, a memory device includes a memory array and a configurable decoder circuit operatively associated with the memory array and configurable to one of a first state or a second state. In the first state, the configurable decoder circuit is operative, responsive to receipt of an address associated with a portion of the memory array, to select the portion while producing a first status signal. In the second state, the configurable decoder circuit is operative, responsive to receipt of an address associated with the portion of the memory array, to prevent selection of the portion while producing a second status signal. The first status signal may indicate, for example, that the portion is valid, while the second status signal may indicate that the portion is invalid.
In other embodiments of the present invention, the memory array includes a plurality of memory blocks. The configurable decoder circuit includes a plurality of configurable block decoder circuits, a respective one of which is coupled to a respective one of the plurality of memory blocks and configurable to one of a first state or a second state. In the first state, a configurable block decoder circuit is operative, responsive to receipt of an address associated with the corresponding memory block, to select the corresponding memory block while producing a first status signal. In the second state, a configurable block decoder circuit is operative, responsive to receipt of an address associated with the corresponding memory block, to prevent selection of the corresponding memory block while producing a second status signal.
In yet another embodiment of the present invention, a configurable block decoder circuit includes an address decoder circuit that receives addresses and that generates an address decoder output signal. The address decoder output signal takes on a first state in response to a particular address and takes on a second state in response to an address other than the particular address. A programmable status signal generating circuit is responsive to the address decoder circuit and includes a programmable element, such as a fuse. The programmable status signal generating circuit is operative to produce a status signal in response to the address decoder output signal, the status signal having one of a first state or a second state depending on a state of the programmable element.
The configurable block decoder circuit may further include a memory block control signal generating circuit responsive to the address decoder circuit and to the status signal generating circuit and operative to produce a memory block control signal therefrom. The memory block control signal takes on a first state when the decoder output signal is in the first state and the status signal is in the first state, and takes on a second state when the address decoder output signal is in the first state and the status signal is in the second state. The corresponding memory block is responsive to the memory block control signal.
The memory device may further include a status output circuit responsive to the address decoder output signal and to the status signal. The status output circuit produces a status output signal that takes on a first state when the address decoder output signal is in the first state and the status signal is in the first state and takes on a second state when the address decoder output signal is in the first state and the status signal is in the second state.
Related memory device operating methods are also discussed.